1. Technical Field
This disclosure relates to semiconductor wafers and more particularly, to a method of maximizing the overall yield of chips per wafer.
2. Description of the Related Art
Semiconductor crystal wafers, such as those made of silicon, are used as a substrate for processing integrated circuit chips. As processing has improved over the years wafer diameters have increased to their current size of approximately 8 inches and greater. Wafers are generally sliced off from a large silicon crystal ingot and are therefore generally circular in shape.
Decreasing feature size for integrated circuit chips has increased the criticality of the planarity of the wafer. Today, with 0.35 micron features becoming widespread, surface planarity is assuming new importance, since it offers the key to boosting performance.
Chemical mechanical polishing (CMP) is a process for improving the surface planarity of a semiconductor wafer and involves the use of mechanical pad polishing systems usually with a silica-based slurry. CMP offers a practical approach to achieving the important advantage of global wafer planarity. However, CMP systems for global planarization have certain limitations. These limitations include low wafer throughput, polished surface non-uniformity and a problem related to polishing uniformity known as "edge exclusion". Edge exclusion occurs when too much of the semiconductor wafer is polished. This causes the edge or outer portion of the wafer to be unusable for integrated circuit fabrication. Wafer polish throughput and polish uniformity are important process parameters, because they also directly affect the number of integrated circuit chips that a fabrication facility can produce for a given period of time.
As mentioned above wafers are circular in shape. Integrated circuit chips are rectangular or square in shape. Since the integrated circuit chips are formed on the wafer, there are areas of the wafer that cannot be used based on the geometry mismatch alone. The area of unused space is further increased due to increased edge exclusion on the wafer. In addition to polishing, edge exclusions can be created by wafer handling devices. An edge exclusion can be defined on a given wafer by handling marks on that wafer. For example, a handling mark that extends further inward from the edge of the wafer than the polishing edge, defines the edge exclusion for that wafer. Edge exclusions tend to measure 2 to 8 millimeters radially outward from the innermost useable diameter to the edge of the wafer.
Typically, methods are used to maximize the amount of available useable area for chips on the semiconductor wafer. One such method attempts to maximize the number of good chips obtainable from a wafer by changing the center point of the wafer map. Referring to FIG. 1, a semiconductor wafer 10 is shown. A wafer map 20 is a layout of integrated circuit chips 12 on a wafer 18 which accounts for cuts between the chips as well. Wafer map 20 is fixed in defining the locations of individual chips 12 relative to one another. Wafer modeling programs are given a wafer map center point 16 and a given edge exclusion as input. The distance between point A and point B is the edge exclusion for wafer 18. An exclusion zone 14 is created at the outside of the wafer. A chip 12 that passes 3 mm past a diameter 22 is considered unusable. The wafer modeling program moves the wafer map by adjusting center point 16 within the region defined by diameter 22 until the maximum number of useable chips is achieved for a given edge exclusion.
Although this method gives the yield for the number of chips with a given edge exclusion, the number of usable chips per wafer may drop off significantly for slightly increased edge exclusions. For example, chips 12a, 12b and 12c are shown with corners in exclusion zone 14. If the edge exclusion is larger these chips may be deemed unusable by the prior art wafer modeling technique. However, some of the chips that extend into exclusion zone 14 may be usable since the yield probability for chips increases with decreasing wafer radius. This means that chips eliminated based on geometry alone may in fact be useable.
Therefore, a need exists for increasing the yield of semiconductor wafers based on the actual yield due to a given edge exclusion.